This invention relates to a semiconductor memory, and more particularly to a technique which is effective when utilized for, e.g., a word line driving circuit in a semiconductor memory which is constructed of MOSFETs (insulated gate type field effect transistors).
As to a word line driving circuit in a semiconductor memory constructed of MOSFETs, there have been proposed, for example, circuit forms as shown in FIGS. 4 and 5 (refer to the official gazette of Japanese patent application Laid-Open No. 55-150189).
The circuit in FIG. 4 is such that a CMOS (complementary MOS) inverter circuit IV for detecting the level of a word line WL is connected to the remote end of the word line WL, and that a MOSFET Q23 is interposed between the word line WL and a power source voltage V.sub.cc. In this circuit, when the potential of the word line WL to be selected has exceeded the logic threshold voltage of the CMOS inverter circuit IV, the output of the CMOS inverter circuit IV is changed to a low level. The P-channel MOSFET Q23 is brought into the "on" state by the low level output of the CMOS inverter circuit IV. As a result, the period of time in which the word line WL (which typically is made of comparatively high resistance polycrystalline silicon) reaches the final arrival level (V.sub.cc) thereof is shortened.
In the circuit of the form shown in FIG. 4, however, when the potential of the selected word line WL is to be lowered to an unselected level (e.g., ground potential), the MOSFET Q23 is held in the "on" state by the output of the CMOS inverter circuit IV. Therefore, a through current flows to the word line WL via the MOSFET Q23, and the potential of the word line is difficult to reduce.
On the other hand, in the circuit shown in FIG. 5, a P-channel MOSFET Q24 and an N-channel MOSFET Q25 for resetting are inserted in series with a MOSFET Q23 and respectively between the MOSFET Q23 and a power source voltage V.sub.cc and between a word line WL and a ground potential point. These MOSFETs Q24 and Q25 are on/off-controlled in synchronism with a word line driving circuit WD. That is, when the word line WL is to be selected, a reset signal P is set to a low level, whereby the MOSFET Q24 is brought into the "on" state, and the MOSFET Q25 into the "off" state. Thus, the illustrated circuit performs the same operation as that of the circuit of FIG. 4 in the selecting mode. When the word line WL is to be set to an unselected level, the reset signal P is changed to a high level. At this time, the MOSFET Q24 is brought into the "off" state, and the MOSFET Q25 is brought into the "on" state, so that the selected word line is quickly changed to the low level. Thus, the problem noted above for the FIG. 4 circuit does not occur.
The circuit of the form in FIG. 5, however, has a large number of elements. Moreover, unless the element size of the MOSFETs Q23 and Q24 is enlarged as compared with that of the MOSFET Q23 in the circuit form of FIG. 4 so as to lower the combined impedance of these MOSFETs connected in series, a rapid rise of the level of the word line is difficult to achieve.
In this regard, in an IC memory, it reduces the occupation area of a memory array to form word lines at the narrowest possible intervals. Accordingly, when it is inevitable to enlarge the sizes of the elements constituting the circuit or to increase the number of the constituent elements as described above, it becomes difficult to arrange circuits in conformity with the word line intervals, especially in an IC memory which is composed of one-element type memory cells. As a result, chip size is enlarged unnecessarily. The problems as described above have been revealed by the inventors' studies regarding the circuit arrangements shown in FIGS. 4 and 5.